This invention relates generally to the field of manufacture of electronic devices. In particular, this invention relates to the manufacture of integrated circuit devices containing low dielectric constant material.
As electronic devices become smaller, there is a continuing desire in the electronics industry to increase the circuit density in electronic components, e.g., integrated circuits, circuit boards, multichip modules, chip test devices, and the like without degrading electrical performance, e.g., crosstalk or capacitive coupling, and also to increase the speed of signal propagation in these components. One method of accomplishing these goals is to reduce the dielectric constant of the interlayer, or intermetal, insulating material used in the components.
A variety of organic and inorganic porous dielectric materials are known in the art in the manufacture of electronic devices, particularly integrated circuits. Suitable inorganic dielectric materials include silicon dioxide and organic polysilicas. Suitable organic dielectric materials include thermosets such as polyimides, polyarylene ethers, polyarylenes, polycyanurates, polybenzazoles, benzocyclobutenes, fluorinated materials such as poly(fluoroalkanes), and the like. Of the organic polysilica dielectrics, the alkyl silsesquioxanes such as methyl silsesquioxane are of increasing importance because of their low dielectric constant.
A method for reducing the dielectric constant of interlayer, or intermetal, insulating material is to incorporate within the insulating film very small, uniformly dispersed pores or voids. In general, such porous dielectric materials are prepared by first incorporating a removable porogen into a B-staged dielectric material, disposing the B-staged dielectric material containing the removable porogen onto a substrate, curing the B-staged dielectric material and then removing the porogen to form a porous dielectric material. For example, U.S. Pat. No. 5,895,263 (Carter et al.) and U.S. Pat. No. 6,271,273 (You et al.) disclose processes for forming integrated circuits containing porous organic polysilica dielectric material. In conventional processes, the dielectric material is typically cured under a non-oxidizing atmosphere, such as nitrogen, and optionally in the presence of an amine in the vapor phase to catalyze the curing process.
After the porous dielectric material is formed, it is subjected to conventional processing conditions of patterning, etching apertures, optionally applying a barrier layer and/or seed layer, metallizing or filling the apertures, planarizing the metallized layer, and then applying a cap layer or etch stop. These process steps may then be repeated to form another layer of the device.
A disadvantage of certain dielectric materials, including organic polysilica dielectric materials, is that they may not provide sufficient resistance to planarization techniques, such as chemical mechanical planarization (“CMP”) used in subsequent manufacturing steps or sufficient resistance to etching, such as oxygen plasma, during photoresist removal from such dielectric materials. One solution to this is to use a layer of a different material atop the dielectric material (i.e. a cap layer) to provide the desired characteristics. Cap layers are useful in both single and dual damascene processes, particularly when porous dielectric materials are used. These layers planarize the surface of the dielectric by filling any surface defects, provide a denser matrix than that of the dielectric so as to seal any porosity having connectivity to the surface of the dielectric film (prevents intrusion of any residues from subsequent processing into the porous dielectric), improve the adhesion with subsequently applied layers of material and provide a hardmask having sufficient resistance to subsequent processing steps and etch differential between it and the underlying porous dielectric layer to allow sequential selective pattern transfers between successive layers of photoimaged pattern, cap layer and dielectric. Suitable cap layer compositions must be able to provide good coating uniformity in the required thickness range (e.g., 100 to 600 Å) and have a low dielectric constant (k≦3.5).
Although certain organic cap layers have recently been recommended, such as poly(arylene ethers), typical cap layers are based on silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride and the like. For example, a conventional poly(arylene ether) dielectric material may have a non-porous methyl silsesquioxane capping layer, or alternatively, a conventional methyl silsesquioxane dielectric layer may have a non-porous poly(arylene ether) capping layer. U.S. patent application Ser. No. 2001/0051447 A1 (Usami) discloses a methyl silsesquioxane dielectric layer having a silicon oxide capping layer to improve the etch resistance.
Chemical vapor deposition (“CVD”) methods are conventionally used to deposit cap layers on the underlying dielectric material. The carrier gas used in the CVD methods can generate amines, which in turn can lead to a poisoning of an overlaid photoresist layer, necessitating the use of either an N2O ashing step of the application of a barrier material between the cap layer and the photoresist. This problem can be eliminated by a spin-on process for the cap layer material. Spin-on methods for depositing cap layers are not without drawbacks. The major problem is assuring a uniform, defect-free coating of the cap layer material, particularly when an inorganic or organic-inorganic material is used as the cap layer. Organic polysilica materials, such as methyl silsesquioxane, often suffer from poor coating uniformity, pinhole defects, and crack formation during curing.
Thus, there is a need for methods for depositing cap layers, particularly organic polysilica cap layers, on a dielectric material that overcome the above problems.